A memory density of a semiconductor memory device as represented by a DRAM (Dynamic Random Access Memory) increases annually along with the progress of microfabrication. However, the actual situation is that along with the progress of miniaturization, the number of defective memory cells included in one chip also increases progressively. Such a defective memory cell is usually replaced by a redundant memory cell, thereby relieving a defective address.
In the case of the DRAM, the defect includes a refresh defect in which information holding time is shorter than a prescribed value (tREF), and a short failure in which a word line and a bit line are shortcircuited due to a manufacturing failure. Regarding the refresh defect, the address can be relieved by replacing a defective memory cell with a redundant memory cell. On the other hand, when the word line and the bit line are shortcircuited, not only the defective word line needs to be replaced with a redundant word line, but also the defective bit line needs to be replaced with a redundant bit line.
When this address replacement is carried out, valid addresses are not allocated to the defective word line and the defective bit line, and, therefore, memory cells corresponding to these addresses are not accessed. In other words, the defective word line is always maintained at an inactive level, and even when any address is supplied, the address is not changed to an active level.
However, because a precharge operation is also carried out to the defective bit line, when the word line and the bit line are shortcircuited, a current flows from the defective bit line at the precharge level to the defective word line at the inactive level. Therefore, there is a problem that total power consumption of chips increases.
As a method of decreasing such a defective current, a method of adding a current limit element to a bit line precharge circuit is proposed (Japanese Patent Application Laid-open No. 2005-243158). However, when the current limit element is added to the bit line precharge circuit, a P-channel MOS transistor included in a sense amplifier is slightly turned on, because the bit line shortcircuited with the word line is always kept at the inactive level of the word line. As a result, although a defective current flowing from the word line to the bit line decreases, a defective current via the sense amplifier occurs. For the same reason, a defective current also flows to a transistor connecting the bit line and a local I/O line.
This problem becomes noticeable when the inactive level of the word line is set to a value below the ground level.
On the other hand, in a shared-sense type DRAM, a transfer switch is often provided between a sense amplifier and a bit line pair. However, in a semiconductor memory device of a type that precharges the sense amplifier and the bit line pair at the same potential, a configuration of precharging within the sense amplifier from the bit line side is mainly employed. Therefore, during the non-access period, the transfer switch always needs to be in the on state. Accordingly, this type of a semiconductor memory device also has a problem that a defective current continues flowing to the sense amplifier via the transfer switch.
As described in Japanese Patent Application Laid-open No. 2002-157885, in a semiconductor memory device of a type that precharges the sense amplifier and the bit line pair at different potentials, the transfer switch is set in the off state during the non-access period. Therefore, defective current does not flow to the sense amplifier in this state. However, the semiconductor memory device of this type has a problem in that the control is complex and the sense operation is slow.